The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Data processing systems that process complex data may perform several operations on the data. For example, systems that process video data and image data (collectively image data) (e.g., digitized photographs) may perform decoding, color space conversion (CSC), filtering, and scaling of the image data. Application specific integrated circuits (ASICs) that are customized to perform the operations may be used to efficiently process the data.
Referring generally to FIGS. 1-3, different data processing system architectures are shown. In FIG. 1, a typical data processing system is shown. In FIG. 2, a data processing system utilizing a pipeline architecture is shown. In FIG. 3, an ASIC that utilizes the pipeline architecture to process image data is shown.
Referring now to FIG. 1, a data processing system (DPS) 10 is shown. The DPS 10 may process different types of data. For example, the DPS 10 may process image data comprising digital graphic images. The image data may conform to the Joint Photographic Experts Group (JPEG) standard. The DPS 10 may be used in handheld devices such as digital cameras and video recorders.
The DPS 10 may comprise a processor 12, a memory control module 13, a system memory 14, an I/O module 15, a data processing module (DPM) 16, and a system bus 18. The processor 12 may execute application programs including graphics-based applications. The memory control module 13 may control the system memory 14 and perform memory management functions. The I/O module 15 may receive image data from a source such as a camera (not shown). The image data may be stored in the system memory 14. The DPM 16 may communicate with the system memory 14 via the system bus 18 and process the image data. The DPM 16 may utilize direct memory access (DMA) to access the system memory 14.
Typically, the DPM 16 may comprise a plurality of processing modules 20-1, 20-2, . . . , 20-N (collectively processing modules 20), where N is an integer greater than or equal to 1. For example, the processing modules 20-1, 20-2, 20-3, and 20-4 may include a decoder module, a CSC module, a filter module, and a scaling module, respectively (all not shown). A first processing module 20-1 comprising the decoder module may receive the image data from the system memory 14. The first processing module 20-1 may decode (i.e., uncompress) the image data and transfer the uncompressed data to the system memory 14. The second processing module 20-2 comprising the CSC module may receive the uncompressed data from the system memory 14. The second processing module 20-2 may perform CSC and transfer the color converted data to the system memory 14.
The processing by remaining processing modules 20 may continue until an Nth processing module 20-N generates and stores a final product of the image data in the system memory 14. For example, the final product be generated by the fourth processing module 20-4 comprising the scaling module and may contain uncompressed, color converted, filtered and scaled image data.
Thus, data may communicate via the system bus 18 2*N times between the system memory 14 and the DPM 16 when the DPM 16 comprises N processing modules 20. Transferring data 2*N times across the system bus 18 may adversely impact the bandwidth of the system bus 18. The impact may be reduced by using the pipeline architecture wherein individual first-in first-out (FIFO) buffers may be provided for each processing module 20. Instead of storing the data processed by each processing module 20 in the system memory 14, the FIFO buffer associated with each processing module 20 can store the data. Additionally, instead of receiving the data processed by a prior processing module 20 from the system memory 14, a subsequent processing module 20 may receive the data from the FIFO buffer of the preceding processing module 20.
Referring now to FIG. 2, a DPS 30 utilizing the pipeline architecture is shown. The DPS 30 may comprise the processor 12, the memory control module 13, the system memory 14, the I/O module 15, and a pipelined DPM 32. The pipelined DPM 32 may comprise a plurality of processing modules 36-1, 36-2, . . . , 36-N (collectively processing modules 36), where N is an integer greater than or equal to 1. The processing modules 36-1, 36-2, . . . , 36-N may include a decoder module, a color space converter module, a filter module, and a scaling module, respectively, where N=4. Each of the processing modules 36 is preceded by a FIFO buffer 34-1, 34-2, . . . , 34-N (collectively FIFO buffers 34), respectively. The FIFO buffer 34-1 is optional. The processing module 36-1 may receive data from the bus and the processing module 36-N may send data to the bus. A FIFO buffer may also be arranged at the output of the processing module 36-N. In other words, FIFO buffers may be arranged between the bus and the first/last modules are optional.
The processing modules 36 and the FIFO buffers 34 may be connected in series as shown and may have standard pipeline communication interfaces. Consequently, data needs to flow through the processing modules 36 and the FIFO buffers 34 (i.e., through the pipeline) in the sequence in which the processing modules 36 and the FIFO buffers 34 are connected.
Typically, the first FIFO module 34-1 may receive the image data from the system memory 14 and output the image data to a first processing module 36-1. The first processing module 36-1 comprising the decoder module may uncompress the image data and transfer the processed data to the second FIFO buffer 34-2. The second FIFO buffer 34-2 may output the uncompressed data to the second processing module 36-2. The second processing module 36-2 comprising the CSC module may perform CSC and output the color converted data to the subsequent FIFO buffer (not shown).
The processing by the remaining processing modules may continue in the sequence until an Nth processing module 36-N generates the final product of the image data. The final product is stored in the system memory 14. The final product may contain uncompressed, color converted, filtered and scaled image data.
Referring now to FIG. 3, an ASIC 50 that utilizes the pipeline architecture to process image data is shown. The ASIC 50 may comprise the processor 12, the memory control module 13, the I/O module 15, a DPM 51, and the system bus 18. The DPM 51 may comprise a decoder module 52, a CSC module 54, a filter module 56, and a scaling module 58 that communicate with the system bus. The ASIC 50 may communicate with the system memory 14 via the memory control module 13. The ASIC 50 may process the image data as follows.
The I/O module 15 may receive a compressed JPEG file. The file may comprise image data containing an 8.5″×11″ color image at 600 dpi. With 24 bit color and 10:1 compression ration, the file size may be 10.1 MB. The file may be stored in the system memory 14. The ASIC 50 may process the file to enlarge, shrink, or rotate the image, or alter colors of the image.
Specifically, the memory control module 13 may read the file from the system memory 14 by performing a DMA operation and forward the data in the file to the decoder module 52. The decoder module 52 may decode the data and generate uncompressed data. The uncompressed data may be very large (e.g., 101 MB). Accordingly, the memory control module 13 may write the 101 MB of uncompressed data back to the system memory 14 by performing a DMA operation. The DMA operation may be complex since the output of JPEG is an 8×8 array of pixels, and the JPEG data is not in raster order unless the DMA operation buffers and writes the array to several memory locations.
Subsequently, the memory control module 13 may perform another DMA operation, read the 101 MB of uncompressed data from the system memory 14, and forward the uncompressed data to the CSC module 54. After performing CSC, the CSC module 54 may forward the color converted data to the filter module 56. The filter module 56 may prepare multiple lines of the color converted data before applying a filter algorithm to the color converted data. A local SRAM buffer 57 associated with the filter module 56 may store the multiple lines during filtering.
After filtering, the filter module 56 may forward the filtered data to the scaling module 58. The scaling module 58 may scale the filtered data up or down depending on whether the image is to be enlarged or reduced. To perform scaling, at least one full line of the filtered data may have to be buffered. A local SRAM buffer 59 associated with the scaling module 58 may store the line during scaling.
After scaling, the memory control module 13 may write the scaled data back to the system memory 14 by performing another DMA operation. The DMA operation may be complex if the image is flipped or rotated, wherein the memory control module 13 receives data from the scaling module 58 and writes it in reverse line order in the system memory 14.
Thus, while the ASIC 50 processes the image data, the memory control module 13 may write large amounts of data twice to the system memory 14 and read the uncompressed data once from the system memory 14. Consequently, the adverse impact on the bandwidth of the system bus 18 may be somewhat reduced when the pipeline architecture is used. Also, the processing modules that process data and perform different functions on the data are connected to one another in a fixed order.